1. Field of the Invention:
The present invention relates generally to a parallel binary adder for carrying out digital addition, and particularly to a parallel binary adder capable of high speed addition for input data having an especially large number of bits.
2. Description of the Prior Art:
FIG. 1 shows a conventional parallel binary adder. This parallel binary adder is for computation of 26 bits addend A (A.sub.25, A.sub.24, A.sub.23 . . . A.sub.2, A.sub.1, A.sub.0) and 26 bits augend B (B.sub.25, B.sub.24, B.sub.23 . . . B.sub.2, B.sub.1, B.sub.0), to produce sums S (S.sub.25, S.sub.24 , S.sub.23 . . . S.sub.2, S.sub.1, S.sub.0) and a carry C.sub.26. Therein, the circuit of FIG. 1 is constituted with CMOS FETs on an IC or LSI.
Numerals 1, 2 and 3 designate EXOR (exclusive OR) gates, and numerals 4, 5, 6 and 7 designate NAND gates, and numeral 8 designates an inverter, which are constituted with CMOS FETs. With respect to the input signals A.sub.0, A.sub.1, A.sub.2, A.sub.3 . . . A.sub.25, input signals B.sub.0, B.sub.1, B.sub.2, B.sub.3 . . . B.sub.25, sum output signals S.sub.0, S.sub.1, S.sub.2 , S.sub.3 . . . S.sub.25, and carry output signals C.sub.0, C.sub.1, C.sub.2, C.sub.3 . . . C.sub.25 and C.sub.26, the circuit of FIG. 1 gives the following relations: ##EQU1## The right-hand circuit i.e., a first order circuit H, operates as half adder, and other circuits, namely, F.sub.1, F.sub.2 . . . F.sub.25, which are constituted in the same circuit configuration as each other, operate as full adders.
Since the EXOR gates have propagation delays corresponding to those of two stages of the general gates, the total addition time of the conventional 26-bit parallel binary adder of FIG. 1 requires propagation delays for 52 stages of gate logic. Generally, an n-bit parallel binary adder requires addition time corresponding to 2n stages of gate logic, and so shortening of the addition time has been sought after.